1. Field of the Invention
The present invention relates generally to integrated circuits. More particularly, it pertains to alignment features for integrated circuit packages.
2. State of the Art
Photolithography and etching are two methods used to fabricate integrated circuits. In photolithography, hundreds of dice are manufactured from a single wafer. After the dice are formed on the wafer, the wafer is segmented into individual units and encapsulated to form a set of packaged integrated circuits.
A percentage of integrated circuits are defective. Some of these parts have defects from the manufacturing process. Others will malfunction within a short period of use. These imperfect integrated circuits are infant mortalities. It is important to isolate these infant mortalities so that they can be discarded prior to sale. The integrated circuit devices are tested using hot and cold conditions to stress the devices and to sort out failures. One step in this process of identifying the infant mortalities is bum-in testing.
In the burn-in test process, integrated circuits are subjected to a high level of stressful conditions, including high temperatures and high voltage. During a typical burn-in test, thousands of integrated circuits are inserted in burn-in boards, which allow electrical connectivity to the individual integrated circuits.
After an extended period of time, the integrated circuits are removed from the stressful conditions and are tested to determine if they are defective. During the testing process, a testing assembly is used to contact conductors on the integrated circuit. For proper testing, each contact on the testing assembly must contact the appropriate conductor on the integrated circuit. If a contact on the testing assembly does not accurately touch the corresponding conductor on the integrated circuit, a variety of problems can arise.
During the testing process, contacts of the testing assembly make physical and electrical contact with the conductors of the integrated circuit. If the integrated circuit is not accurately aligned with the testing assembly, the accuracy of the physical contact is jeopardized. Misaligned contacts of the testing assembly can deform the conductors and damage the integrated circuit.
Additionally, misaligned contacts of the testing assembly may not permit sufficient electrical contact between the contacts of the testing assembly and the conductors of the integrated circuit. This results in integrated circuits being falsely flagged as defects and unnecessarily increases production costs. Furthermore, integrated circuits are becoming more complex with more capabilities. As a result, leads on lead frames are being placed closer and closer together, which further complicates accurate testing procedures.
Accordingly, what is needed is a better way to align integrated circuit packages during the testing process.